The previous section showed showed that modern compilers can transform some constructs such as simple-sum-loops to vectorized versions already. The optimization potential is not yet exhausted, however, as in this specific case we might do better by adding more AVX register accumulators.
Singlethreaded AVX
#include <immintrin.h>
inline double dotproduct_avx(size_t n, double* a, double* b){
size_t blocks_end = n-static_cast<int>(n&15);
double acc = 0;
size_t i = 0;
if (blocks_end != n){
__m256d sum1 = _mm256_setzero_pd();
__m256d sum2 = _mm256_setzero_pd();
__m256d sum3 = _mm256_setzero_pd();
__m256d sum4 = _mm256_setzero_pd();
for (i=0;i<blocks_end;i+=16){
__m256d x = _mm256_loadu_pd(a);
__m256d y = _mm256_loadu_pd(a+4);
__m256d z = _mm256_loadu_pd(a+8);
__m256d w = _mm256_loadu_pd(a+12);
__m256d k = _mm256_loadu_pd(b);
__m256d r = _mm256_loadu_pd(b+4);
__m256d p = _mm256_loadu_pd(b+8);
__m256d m = _mm256_loadu_pd(b+12);
__m256d xk = _mm256_mul_pd(x,k);
__m256d yr = _mm256_mul_pd(y,r);
__m256d zp = _mm256_mul_pd(z,p);
__m256d wm = _mm256_mul_pd(w,m);
sum1 = _mm256_add_pd(sum1,xk);
sum2 = _mm256_add_pd(sum2,yr);
sum3 = _mm256_add_pd(sum3,zp);
sum4 = _mm256_add_pd(sum4,wm);
a += 16;
b += 16;
}
__m256d sum1_plus_sum2 = _mm256_add_pd(sum1,sum2);
__m256d sum2_plus_sum3 = _mm256_add_pd(sum3,sum4);
__m256d sum1_sum2_plus_sum3_sum4 = _mm256_add_pd(sum1_plus_sum2,sum2_plus_sum3);
__m128d sum1_sum2_plus_sum3_sum4_low = _mm256_castpd256_pd128(sum1_sum2_plus_sum3_sum4);
__m128d sum1_sum2_plus_sum3_sum4_high = _mm256_extractf128_pd(sum1_sum2_plus_sum3_sum4,1);
__m128d sum = _mm_add_pd(sum1_sum2_plus_sum3_sum4_low,sum1_sum2_plus_sum3_sum4_high);
__m128d shuffled_sum = _mm_shuffle_pd(sum,sum,0b01);
__m128d result = _mm_add_pd(sum,shuffled_sum); //result is stored in lower and higher register halves
acc+=_mm_cvtsd_f64(result);
}
blocks_end = n-static_cast<int>(n&7);
if (blocks_end != n){
__m256d sum1 = _mm256_setzero_pd();
for (;i<blocks_end;i+=8){
__m256d x = _mm256_loadu_pd(a);
__m256d y = _mm256_loadu_pd(a+4);
__m256d z = _mm256_loadu_pd(b);
__m256d w = _mm256_loadu_pd(b+4);
__m256d xz = _mm256_mul_pd(x,z);
__m256d yw = _mm256_mul_pd(y,w);
__m256d xz_plus_yw = _mm256_add_pd(xz,yw);
sum1 = _mm256_add_pd(sum1,xz_plus_yw);
a += 8;
b += 8;
}
__m128d sum1_low = _mm256_castpd256_pd128(sum1);
__m128d sum1_high = _mm256_extractf128_pd(sum1,1);
__m128d sum = _mm_add_pd(sum1_low,sum1_high);
__m128d shuffled_sum = _mm_shuffle_pd(sum,sum,0b01);
__m128d result = _mm_add_pd(sum,shuffled_sum); //result is stored in lower and higher register halves
acc += _mm_cvtsd_f64(result);
}
while (i<n){
acc += (*a)*(*b);
a++;
b++;
i++;
}
return acc;
}
This leads to the following result:
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This is around half the time than the running time than the previous version. Again, it is worthwhile to calculate the throughput:
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And cropped:
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At 2 million elements the throughput for double sized numbers at 28.29 GB/s is faster than the naive version which for this size ran at 13.36 GB/s.
In fact, it is even higher than the previous overall peak which was 23.3 GB/s. The difference becomes even more stark for smaller sizes:
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For double sized floating points at 4096 overall elements 198.63 GB/s are achieved! As the L1D cache of this system is 32 KiB large it can be assumed that all 4096 8 byte sized elements fit into L1D. A throughput of
198.63 GB/s is close to the theoretical 256 GB/s L1D bandwidth calculated previously limit. The vectorized operations lend themselvs well to utilize the maximum cache throughput as well as possible.
For example, a VMOVAPS instruction used in aligned loads for _mm256_loadu_pd can load multiple elements in a single cycle.
Multithreaded AVX
The AVX dotproduct can be parallelized further by using multiple cores:
template<class T>
T dotproduct_parallel(size_t n_threads, size_t block_size, size_t n, T (*f)(size_t, T*, T*), T* x, T* y){
if (n == 0){
return T(0);
}
size_t blocks_used=(n+block_size-1)/block_size;
size_t blocks_per_thread=blocks_used/n_threads;
int blocks_per_thread_remainder=blocks_used%n_threads;
size_t threads_used=(blocks_per_thread==0)?blocks_per_thread_remainder:n_threads;
std::vector<std::thread> ts(threads_used-1);
std::vector<T> res(threads_used-1);
auto dp=[&f](T& res, size_t n, T* a, T* b){
res=f(n,a,b);
};
for (size_t i=0;i<threads_used-1;i++){
size_t step=(blocks_per_thread_remainder>0)?block_size*(blocks_per_thread+1):block_size*blocks_per_thread;
ts[i]=std::thread(dp,std::ref(res[i]),step,x,y);
x+=step;
y+=step;
blocks_per_thread_remainder--;
n-=step;
}
T sum=f(n,x,y);
for (auto& t:ts){
t.join();
}
for (auto s:res){
sum+=s;
}
return sum;
}
This adds 2 new parameters that affect performance: The number of utilized threads n_threads and the minimum number of elements block_size each thread works on. For ease
of comparison block_size = 50000. In a more elaborate performance optimization this value would be more careful chosen to balance the set up cost for each thread and minimize false sharing at a thread's margin of computation range.
Now the optimal number of threads for this system can be found:
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It must be kept in mind that with the current block_size a thread is only launched if it can be fed with a minimum of 500000 elements. For example, to utilize 40 threads a minimum size of size of 2 million elements is needed.
The plot shows that all the results are close. The nonconstant overhead of launching threads contributes to the variation observed.
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In the float benchmark all the results are well within the margin of variation too.
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While the throughput for smaller array sizes remains, albeit with different peaks, similar in its qualitative behaviour, large arrays benefit reaching 31.71 GB/s at 268M double sized numbers. This is 1.28 times as much as 24.66 GB/s which was reached in a single threaded environment. Nevertheless, the program is memory bandwidth starved and the theoretical wall of 42.656 GB/s on this computer for large arrays cannot be exceeded. The AVX code could even be further optimized via loop unrolling techniques (benefit questionable, tested it out), using 256 bit wide fused multiply add instructions (no benefit, tested it out) or even AVX512 (which this processor does not support).
Special Case Optimization: x = y
If both input vectors x,y are the same (as happens often during e.g. normalization operations), all registers can be dedicated to reducing a single vector:
inline double dotproduct_sum_of_squares<0,0>(size_t n, double* a){
size_t blocks_end = n-static_cast<size_t>(n&31);
double acc = 0.0;
size_t i = 0;
if (blocks_end != n){
__m256d sum1= _mm256_setzero_pd();
__m256d sum2= _mm256_setzero_pd();
__m256d sum3= _mm256_setzero_pd();
__m256d sum4= _mm256_setzero_pd();
__m256d sum5= _mm256_setzero_pd();
__m256d sum6= _mm256_setzero_pd();
__m256d sum7= _mm256_setzero_pd();
__m256d sum8= _mm256_setzero_pd();
for (;i<blocks_end;i+=32){
__m256d x=_mm256_loadu_pd(a);
__m256d y=_mm256_loadu_pd(a+4);
__m256d z=_mm256_loadu_pd(a+8);
__m256d w=_mm256_loadu_pd(a+12);
__m256d k=_mm256_loadu_pd(a+16);
__m256d r=_mm256_loadu_pd(a+20);
__m256d p=_mm256_loadu_pd(a+24);
__m256d m=_mm256_loadu_pd(a+28);
__m256d xx= _mm256_mul_pd(x,x);
__m256d yy= _mm256_mul_pd(y,y);
__m256d zz= _mm256_mul_pd(z,z);
__m256d ww= _mm256_mul_pd(w,w);
__m256d kk= _mm256_mul_pd(k,k);
__m256d rr= _mm256_mul_pd(r,r);
__m256d pp= _mm256_mul_pd(p,p);
__m256d mm= _mm256_mul_pd(m,m);
sum1= _mm256_add_pd(sum1,xx);
sum2= _mm256_add_pd(sum2,yy);
sum3= _mm256_add_pd(sum3,zz);
sum4= _mm256_add_pd(sum4,ww);
sum5= _mm256_add_pd(sum5,kk);
sum6= _mm256_add_pd(sum6,rr);
sum7= _mm256_add_pd(sum7,pp);
sum8= _mm256_add_pd(sum8,mm);
a+=32;
}
__m256d xx_plus_yy=_mm256_add_pd(sum1,sum2);
__m256d zz_plus_ww=_mm256_add_pd(sum3,sum4);
__m256d kk_plus_rr=_mm256_add_pd(sum5,sum6);
__m256d pp_plus_mm=_mm256_add_pd(sum7,sum8);
__m256d xx_yy_plus_zz_ww=_mm256_add_pd(xx_plus_yy,zz_plus_ww);
__m256d kk_rr_plus_pp_mm=_mm256_add_pd(kk_plus_rr,pp_plus_mm);
__m256d xx_yy_zz_ww_plus_kk_rr_pp_mm=_mm256_add_pd(xx_yy_plus_zz_ww,kk_rr_plus_pp_mm);
__m128d xx_yy_zz_ww_plus_kk_rr_pp_mm_low=_mm256_castpd256_pd128(xx_yy_zz_ww_plus_kk_rr_pp_mm);
__m128d xx_yy_zz_ww_plus_kk_rr_pp_mm_high=_mm256_extractf128_pd(xx_yy_zz_ww_plus_kk_rr_pp_mm,1);
__m128d sum=_mm_add_pd(xx_yy_zz_ww_plus_kk_rr_pp_mm_low,xx_yy_zz_ww_plus_kk_rr_pp_mm_high);
__m128d shuffled_sum=_mm_shuffle_pd(sum,sum,0b01);
__m128d result=_mm_add_pd(sum,shuffled_sum); //result is stored in lower and higher register halves
acc+=_mm_cvtsd_f64(result);//
}
while (i<n){
acc+=(*a)*(*a);
a++;
i++;
}
return acc;
}
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At first glance, while the running time is lower indeed it has not consistently halved, leading to a slight decrease in throughput as well. This shows that looking at throughput only to judge an optimization's benefit is not enough, as this optimization is still well worth it.